Communication apparatus, communication method, image forming apparatus utilizing such method, unit connected to image forming apparatus and image forming system

ABSTRACT

A sampling unit samples plural input signals, and detects a point (change point) at which one of the sampled input signals shows a change in the logic level. In case the logic level after the detection of the change point continues for a predetermined time, the plural sampled data are respectively latched or outputted after the lapse of the predetermined time, and, in any other timing, the sampled data are held, thereby obtaining plural noise-eliminated signals. One of the plural input signals is a clock signal, and, in case of data transmission in synchronization with such clock signal, the transmission is executed with a timing synchronized with the noise-eliminated signal. The predetermined time is selected equal to or less than ¼ of the cycle period of the communication synchronization clock signal.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a communication apparatus, a communication method, an image forming apparatus utilizing the same, a unit connected to the image forming apparatus and an image forming system.

[0003] 2. Related Background Art

[0004] At first there will be briefly explained a noise elimination apparatus utilizing a digital noise filter of digital input. As disclosed for example in Japanese Patent Application Laid-Open No. 58-205327, there is already known a noise elimination apparatus utilizing a digital noise filter, in which the state of the input signal is monitored plural times at a predetermined time interval, and the state of the signal is captured only when, after a change in the state of the signal, the changed state continues for a predetermined time. Also there is disclosed, for example in Japanese Patent Application Laid-Open No. 53-142157, a noise elimination apparatus with a variable digital noise filter capable of arbitrarily setting the observation time for the continuation of the state of the signal after the change thereof. The variable digital noise filter is advantageous in that the time not sensing the noise can be arbitrarily set according to the magnitude and time of the noise to be eliminated. It is effective in case the noise situation is not clear in the location where the noise elimination apparatus is to be installed or in case the noise situation changes from time to time.

[0005]FIG. 10 is a block diagram showing an example of the noise elimination apparatus utilizing the variable digital noise filter. A noise elimination unit 114 is provided with a sampling unit 108 for sampling an input signal at the timing of an input reference clock, a change point detection unit 109 for detecting a point of change to a low logic level if the logic level prior to the point of observation is high, or to a high logic level if the logic level prior to the point of observation is low, and a same level continuation observation unit 110 for observing whether the changed logic level continues for a predetermined time after the change point is detected by the change point detection unit 110. The same level continuation observation unit 110 observes, in case the logic level changes from high to low, whether the low logic level continues for a predetermined time after the state change thereto, or, in case the logic level changes from low to high, whether the high logic level continues for a predetermined time after the state change thereto. It is thus rendered possible to identify whether the aforementioned change of the logic level has resulted from an actual signal or from a noise, because the noise shows rapid repetitions of high and low logic levels and cannot maintain, for the predetermined time, the changed logic level after the change thereof.

[0006] The noise elimination unit is further provided with a same level continuation observation time setting unit 111 for setting or changing the predetermined time for observing the same level continuation observation unit 110. Such unit allows to set an appropriate predetermined time in another system with a different reference clock or with a different noise environment, thereby achieving noise elimination more effectively. The noise elimination unit 114 is further provided with a data capture timing generation unit 112 for determining the timing of capturing the input signal in response to the result of the same level continuation observation unit 110, and a latch/hold unit 113 for latching or holding the actually sampled input signal in response to the result of the data capture timing generation unit 112. In case the input signal, after the change thereof, maintains a same logic level for the predetermined time, the latch/hold unit 113 latches the sampling data as effective data, after the lapse of the predetermined time. Otherwise it holds the data of its own by feedback of such data. It is thus rendered possible to prevent easy entry of the noise into the circuit.

[0007]FIG. 11 shows an example of an image forming apparatus capable of two-sided printing. An image forming apparatus 200, capable of two-sided printing by mounting a two-sided unit 168, is provided with a scanner unit 161, a photosensitive member 162 to be exposed to a laser unit emitted from the scanner unit 161, a developing unit 163 for developing a latent image formed by exposure on the photosensitive member 162, a transfer belt 165 for transferring an image onto a recording sheet 164, a fixing unit 166 for fixing the transferred image to the recording sheet 164, a cassette 167 holding a stack of the recording sheets 164, and an engine control unit 101 (to be explained later) for controlling these component units. Also the two-sided unit 168 for enabling two-sided printing on the recording sheet 164 is provided with a two-sided control unit 169 (to be explained later) for controlling such two-sided unit 168.

[0008]FIG. 12 is a block diagram showing connection of the engine control unit 101 and the two-sided unit control unit 169 by bidirectional clock-synchronized serial communication. Each of the engine control unit 101 and the two-sided unit control unit 169 emits and receives various unrepresented signals, and the engine control and the two-sided unit control are achieved by monitoring the states of these input signals. (In FIG. 12, there are only shown a communication synchronization clock CLK, transmission data T×D and reception data R×D.) In case a two-sided printing is instructed, the engine control unit 101 and the two-sided unit control unit 169 execute serial communication to share the controls whereby the two-sided unit control unit 169 controls the two-sided unit 168 while the engine control unit 101 controls other components. The engine control unit 101 is provided with a master CPU 102 including a serial communication unit 103 for executing clock synchronized communication with the two-sided unit control unit 169, while the two-sided unit control unit 169 is provided with a slave CPU 105 including a serial communication unit 106 for executing clock synchronized communication with the engine control unit 101.

[0009] In the following there will be explained, with reference to FIGS. 13A and 13B, a communication method of exchanging command and status by the serial communication unit 103 of the master CPU 102 and the serial communication unit 106 of the slave CPU 103.

[0010]FIG. 13A is a view showing the relationship between clock signal and data in the bidirectional clock synchronized communication. In synchronization with the downshift of a clock signal transmitted by the master CPU 102, the data transmitting side transmits data of 8 bits, from the LSB (least significant bit) to the MSB (most significant bit). On the other hand, in synchronization with the upshift of the clock signal transmitted by the master CPU 102, the receiving side receives the data of 8 bits from the LSB (least significant bit) to the MSB (most significant bit).

[0011]FIG. 13B is a timing chart showing the state of communication between the master CPU 102 and the slave CPU 105. In FIG. 13B, CLK, T×D and R×D are names from the side of the master CPU 102, and respectively indicate a communication synchronization clock, transmission data and reception data. At first, in synchronization with the downshift of the communication synchronization clock, the master CPU 102 transmits the transmission data T×D. Based on the SLK and T×D transmitted from the master CPU 102, the slave CPU 105 receives the reception data of 8 bits in synchronization with the upshift of the communication synchronization clock. Then the slave CPU 105 transmits the transmission data of 8 bits in synchronization with the downshift of the communication synchronization clock. The transmission data from the slave CPU 105 are the reception data R×D seen from the master CPU 102, which thus receives the reception data of 8 bits in synchronization with the upshift of the communication synchronization clock. In this manner the transmission data T×D and the reception data R×D are emitted and received in synchronization with the communication synchronization clock emitted by the master CPU 102. The engine control unit 101 and the two-sided unit control unit 169 are respectively provided with unrepresented input units for plural input signals, and an above-described noise elimination apparatus is required for such input unit in order not to capture erroneous digital data. Particularly in the bidirectional clock synchronized serial communication, if a noise is superposed on the communication synchronization clock signal, the slave side which receives the data in synchronization with the communication synchronization clock executes the data capture at a wrong timing, resulting in frequency reception errors. Also the reception data will involve a reception error if a noise is generated at the upshift of the communication synchronization clock. Similarly, also in the master side, there will result a reception error if a noise is generated at the upshift of the communication synchronization clock.

[0012] Thus, in the clock synchronized serial communication, a transmission error or a reception error will result in the data if a noise is superposed on the communication synchronization clock or on the transmission or reception data. Particularly if a noise is superposed on the communication synchronization clock signal, the slave side which receives the data in synchronization with the communication synchronization clock executes the data capture at a wrong timing, resulting in frequency reception errors. Also the reception data will involve a reception error if a noise is generated at the upshift of the communication synchronization clock.

[0013] In the clock synchronized serial communication, as the receiving side often recognizes erroneous data because of the noise, there has been adopted a measure as shown in FIG. 15. More specifically, in such measure, a low-pass filter consisting of a resistor 51 and a capacitor 52 is provided on each line connecting the engine control unit 101 and the two-sided unit control unit 169. Such low-pass filter has a cutoff frequency fc=1/(2πRC) and can attenuate and eliminate the noise of a frequency higher than such cutoff frequency.

[0014] In case the noise elimination apparatus of the variable digital noise filter type is provided on each of the input units for the plural digital inputs, as shown in FIG. 14, there will be required, corresponding to the number of the input units, the variable timing generation units for observing the state of the input signal plural times at a predetermined time interval and capturing the signal only if, after the change in the state of the signal, the changed state continues for a predetermined time, whereby the magnitude of circuitry becomes inevitably large.

[0015] Also in case data signal is transmitted from the slave side in synchronization with the clock signal outputted from the master side as in the bidirectional clock synchronized serial communication, the delay in time is accumulated, in the course of communication, by the forward signal (clock signal) and the returns signal (data signal), whereby the timing of receiving the data signal at the master side may be perturbed. Consequently, in case a delay in the communication is possible, the noise elimination apparatus of the variable digital noise filter type cannot be installed, so that the digital noise filter of high noise eliminating effect cannot be adopted. Stated differently, the conventional noise elimination apparatus of the variable digital noise filter type as shown in FIG. 10 has a wide application because the aforementioned predetermined time can be selected according to the desired level of noise elimination, but, because the aforementioned predetermined time can be arbitrarily selected, the reception timing for the data signal at the master side may be perturbed if such time is selected excessively large. For this reason, the variable digital noise filter has not been employed in practice, and the noise elimination has been achieved by the analog filter of a predetermined cutoff frequency fc as shown in FIG. 15. The cutoff frequency fc is determined as 1/2πRC by a preset resistor R and a preset capacitor C, whereby the noises of higher frequencies are eliminated by attenuation.

SUMMARY OF THE INVENTION

[0016] An object of the present invention is to remove the above-described drawbacks.

[0017] Another object of the present invention is to provide a communication apparatus, a communication method, an image forming apparatus utilizing such method, a unit connected to the image forming apparatus and an image forming system, capable of securely achieving noise elimination in the digital signal without increasing the magnitude of the circuitry.

[0018] Still another object of the present invention is to provide a communication apparatus, a communication method, an image forming apparatus utilizing such method, a unit connected to the image forming apparatus and an image forming system, capable, in case of data transmission in synchronization with a clock signal transmitted from a partner, of securely transmitting the signal to be transmitted even if a noise is superposed on the clock signal, without increasing the magnitude of the circuitry.

[0019] The above-mentioned objects can be attained, according to the present invention, by a communication apparatus comprising:

[0020] a first input means for inputting a first digital signal;

[0021] a second input means for inputting a second digital signal synchronized with the first digital signal;

[0022] an observation means for observing the state of the first digital signal;

[0023] a first digital signal capture means for capturing the first digital signal, in case the state of the first digital signal changes, according to the state of the first digital signal for a predetermined time thereafter; and

[0024] a second digital signal capture means for capturing the second digital signal at the capture timing of the first digital signal by the first digital signal capture means.

[0025] Preferably the first digital signal is a clock signal, and the second digital signal is a data signal transmitted in synchronization with the clock signal. Also preferably the communication apparatus further comprises setting means for variably setting the aforementioned predetermined time.

[0026] Also according to the present invention, there is provided an image forming apparatus provided with the above-described communication apparatus for communicating with a unit connected to the image forming apparatus. Also according to the present invention, there is provided a unit connected to an image forming apparatus and provided with the above-described communication apparatus for communicating with the image forming apparatus. Also according to the present invention, there is provided an image forming system which includes an image forming apparatus and a unit connected thereto and in which at least either of the image forming apparatus and the unit is provided with the above-described communication apparatus for executing communication between the image forming apparatus and the unit. Preferably the aforementioned unit is at least one of a two-sided unit, and an MPT (multipurpose tray) and an envelope feeder, and the image forming apparatus communicates with a unit or with plural units.

[0027] Also according to the present invention, there is provided a communication method in a communication apparatus including first input means for inputting a first digital signal and second input means for inputting a second digital signal synchronized with the first digital signal, the method comprising:

[0028] an observation step of observing the state of the first digital signal;

[0029] a first digital signal capture step of capturing the first digital signal, in case the state of the first digital signal changes, according to the state of the first digital signal for a predetermined time thereafter; and

[0030] a second digital signal capture step of capturing the second digital signal at the capture timing of the first digital signal by the first digital signal capture step.

[0031] Preferably the first digital signal is a clock signal and the second digital signal is a data signal transmitted in synchronization with the clock signal.

[0032] According to the present invention, there is provided another communication apparatus capable of transmitting a data signal in synchronization with an input clock signal, the apparatus comprising:

[0033] a clock signal input means for inputting a clock signal;

[0034] a data signal transmission means for transmitting a data signal;

[0035] an observation means for observing the state of the clock signal; and

[0036] a clock signal capture means for capturing the clock signal, in case the state of the clock signal changes, based on the state of the clock signal for a predetermined time thereafter.

[0037] Wherein the data signal transmission means transmits the data signal in synchronization with the clock signal captured by the clock signal capture means.

[0038] Preferably the aforementioned predetermined time is at least selected not exceeding ¼ of the cycle period of the clock signal. Also preferably the communication apparatus further comprises setting means for variably setting the aforementioned predetermined time.

[0039] Also according to the present invention, there is provided an image forming apparatus provided with the above-described communication apparatus for communicating with a unit connected to the image forming apparatus. Also according to the present invention, there is provided a unit connected to an image forming apparatus and provided with the above-described communication apparatus for communicating with the image forming apparatus. Also according to the present invention, there is provided an image forming system which includes an image forming apparatus and a unit connected thereto and in which at least either of the image forming apparatus and the unit is provided with the above-described communication apparatus for executing communication between the image forming apparatus and the unit. Preferably the aforementioned unit is at least one of a two-sided unit, an MPT and an envelope feeder, and the image forming apparatus communicates with a unit or with plural units.

[0040] Also according to the present invention, there is provided another communication method for use in a communication apparatus including digital signal input means for inputting a digital signal and data signal transmission means for transmitting a data signal, the method comprising:

[0041] an observation step of observing the state of the aforementioned first digital signal;

[0042] a clock signal capture step of capturing the clock signal, in case the state of the clock signal changes, based on the state of the clock signal for a predetermined time thereafter; and

[0043] a data signal transmission step of transmitting the data signal in synchronization with the clock signal captured in the clock signal capture step.

[0044] Preferably the communication method further comprises a data signal transmission step of transmitting the data signal in synchronization with the clock signal captured in the clock signal capture step.

[0045] Preferably the aforementioned predetermined time is at least selected not exceeding ¼ of the cycle period of the clock signal.

[0046] Still other objects of the present invention, and the features thereof, will become fully apparent from the following description to be taken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0047]FIG. 1 is a view showing an example of the configuration of a variable digital noise filter embodying the present invention;

[0048]FIG. 2 is a view showing the relationship between plural input signals superposed with noises F and G, and the plural input signals after the elimination of the noises;

[0049]FIG. 3 is a block diagram showing the configuration of a noise elimination unit 7;

[0050]FIG. 4 is a circuit diagram showing the configuration of the noise elimination unit 7;

[0051]FIG. 5 is a view showing the configuration of an image forming apparatus provided with a noise elimination apparatus for serial communication constituting an embodiment of the present invention;

[0052]FIG. 6 is a block diagram showing the connection between an engine control unit 1 and a two-sided unit control unit 69 by serial communication;

[0053]FIG. 7A is a view showing the relationship between a clock signal and data signals in a clock synchronized serial communication in which noises A and B are superposed in a period in which a communication synchronization clock signal is not generated;

[0054]FIG. 7B is a view showing the relationship between a clock signal and data signals in a clock synchronized serial communication in which noises C and D are superposed in a period in which the communication synchronization clock signal is generated;

[0055]FIG. 7C is a view showing the relationship between a clock signal and data signals in a clock synchronized serial communication in which a noise E is superposed in a period in which the communication synchronization clock signal maintains a same logic level after a change therein;

[0056]FIG. 8 is a timing chart showing the communication state between a master CPU 2 and a slave CPU 6 in a bidirectional clock synchronized serial communication;

[0057]FIG. 9 is a block diagram showing connection by serial communication between an engine control unit 101 and a two-sided unit control unit 169;

[0058]FIG. 10 is a block diagram showing the configuration of a noise elimination unit 114;

[0059]FIG. 11 is a view showing the configuration of an image forming apparatus;

[0060]FIG. 12 is a block diagram showing connection by serial communication between an engine control unit 101 and a two-sided unit control unit 169;

[0061]FIG. 13A is a timing chart showing the relationship between a clock signal and a data signal in a clock synchronized serial communication;

[0062]FIG. 13B is a timing chart showing the communication state between a master CPU 102 and a slave CPU 105;

[0063]FIG. 14 is a view showing a configuration provided with a plurality of conventional digital noise filters; and

[0064]FIG. 15 is a block diagram showing the connection between the engine control unit 101 and the two-sided unit control unit 169 by serial communication.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0065] Now the present invention will be clarified in detail by preferred embodiments thereof, with reference to the accompanying drawings.

[0066] [First Embodiment]

[0067]FIG. 1 shows an example of the configuration in which the present invention is applied to a communication apparatus provided with plural input units.

[0068] In the present embodiment, there will be explained a case in which three input signals, namely input 1 (IN1), input 2 (IN2) and input 3 (IN3), are input into a CPU 2. These input signals are input into the CPU 2 after noise elimination respectively by latch/hold circuits 53-a, 53-b, 53-c. A variable timing generator 54 observes whether the state of the digital data of IN1 is maintained for a predetermined time after a change in the state, and generates a timing signal after the lapse of the predetermined time. In the variable timing generator 54, the predetermined continuation observation time can be arbitrarily set from the CPU 2. The output of the variable timing generator 54 is used as control signals for the latch/hold circuits 53-a, 53-b, 53-c for IN1, IN2, IN3.

[0069] The input frequencies of these input signals are in the order of IN3<IN2<IN1, thus being highest in the signal IN1. Also the change points of the digital data IN2 and IN3 are included in the change point of the digital data IN1. In such case, according to the present invention, the latch/hold 1 control signal (LATCH*/HOLD1) outputted from the variable timing generator 54 is a control signal generated by the signal IN1 and is also used as the latch/hold control signals for the inputs IN2 and IN3.

[0070] Now reference is made to FIG. 2 for explaining in detail the function of noise elimination according to the present invention. FIG. 2 shows a case where noises F and G are superposed. The noises F and G are superposed similarly on the signals IN1, IN2 and IN3 if they are assumed to have a same input path. In case the signal IN1 is superposed with the noises as shown in FIG. 2, the control signal of the variable timing generator 54 assumes a state indicated by LATCH*/HOLD 1 shown in FIG. 2. Therefore, after the change point of the digital signal IN1 in the absence of the noise F or G, the data is captured after the lapse of the predetermined time, so that the LATCH*/HOLD1 signal assumes the low level state. In the presence of the noise F, the data is captured after the lapse of the predetermined time from the end of the noise F, so that the LATCH*/HOLD1 signal assumes the low level state. Also in the presence of the noise G, the digital signal IN1 is disregarded as it does not maintain a same state for the predetermined time after the change of the state. The LATCH*/HOLD1 signal thus prepared from the signal IN1 is used for obtaining a noise-eliminated input signal NIN1 (New IN1), which is input into the CPU 2.

[0071] The LATCH*/HOLD1 signal is also used as a control signal for noise elimination of the signals IN2 and IN3. The frequencies of the signals IN2, IN3 are lower than that of the signal IN1, and the change points of the digital data IN2, IN3 are contained in those of the digital data IN1. Therefore the LATCH*/HOLD1 signal allows to latch the digital data without missing the change points of the digital data IN2 and IN3, thereby achieving noise elimination. According to the present invention, the variable timing generator 54 need not be provided on each of the input units for the plural digital input signals, whereby the circuitry can be made smaller.

[0072] [Second Embodiment]

[0073]FIG. 3 is a block diagram showing an example of the configuration of an embodiment 2 applicable for example to the slave side of a clock synchronized serial communication apparatus.

[0074] A noise elimination unit 7 is provided with a sampling unit 8 for sampling an input signal DATA1 with the timing of an input reference clock signal, a change point detection unit 9 for detecting the change point of the signal sampled by the sampling unit 8, namely a point of change to a LOW logic level from a HIGH logic level prior to the point of observation or to a HIGH logic level from a LOW logic level prior to the point of observation, and a same level continuation observation unit 10 for observing whether the changed logic level, after the detection of the change point by the change point detection unit 9, is maintained for a predetermined time. The same level continuation observation unit 10 observes, in case of a change from the HIGH logic level to the LOW logic level, whether the LOW logic level after the change thereto is maintained for the predetermined time, or, in case of a change from the LOW logic level to the HIGH logic level, whether the HIGH logic level after the change thereto is maintained for the predetermined time. It is thus rendered possible to identify whether the aforementioned change in the logic level has resulted from an actual change in the signal or from a noise, because the logic level does not maintain the state after the change for the predetermined time as the high and low logic levels are repeated rapidly in case of a noise.

[0075] The same level continuation observation unit 10 is provided with a same level continuation observation time setting unit 11 for setting or changing the predetermined observation time of the same level continuation observation unit 10. It is thus rendered possible to set an appropriately observation time in another system with a different reference clock signal or with a different noise environment, thereby achieving noise elimination more effectively. The noise elimination unit 7 is further provided with a data capture timing generation unit 12 for determining the capture timing for the input signal DATA1 according to the result of the same level continuation observation unit 10, and a latch/hold unit 13 for latching or holding the actually sampled input signal DATA1 according to the result of the data capture timing generation unit 12. The latch/hold unit 13, in case the input signal DATA1 changes and thereafter maintains a same logic level for the predetermined time, latches the sampled data as effective after the lapse of the predetermined time, but, otherwise holds the data of its own by feedback. It is thus rendered possible to prevent easy entry of the noise into the circuits.

[0076] In the present embodiment, the change point detection unit 9, the same level continuation observation unit 10 and the data capture timing generation unit 12 are used in common for the input signals DATA1 and DATA2, and such units are not separately provided for the signal DATA2.

[0077] In the present embodiment there will be explained a case where the input signal DATA1 is a communication synchronization clock signal, and the input signal DATA2 is a reception data signal transmitted in synchronization with the communication synchronization clock signal. In the present embodiment, the frequency of the reception data (input signal DATA2) is lower than that of the communication synchronization clock signal (input signal DATA1), and the change point in the logic level of the reception data (input signal DATA2) always lies at the downshift of the communication synchronization clock signal (input signal DATA1). Consequently the capture of the reception data (input signal DATA2) at a determined capture timing does not result in an erroneous capture of the reception data (input signal DATA2), by checking the change point of the logic level of the communication synchronization clock signal (input signal DATA1) and accordingly determining the capture timing of the reception data (input signal DATA2).

[0078] Also the environment of noise generation is same for the synchronization clock signal (input signal DATA1) and the reception data (input signal DATA2), so that, if a noise is present in either, it is also present in the other. Stated differently, the noise is assumed to be present similarly on both signals at the same time. Therefore, it is rendered possible to obtain the noise-eliminated reception data (input signal DATA2) by determining the capture timing therefor in the sequence for at least eliminating the noise superposed with the communication synchronization clock signal (input signal DATA1). In the foregoing there has been explained a case involving a reception data, but there may be employed plural reception data.

[0079]FIG. 4 is a circuit diagram showing an example of the noise elimination unit 7 shown in FIG. 3. The present example is composed of a synchronization circuit in order to facilitate formation of an LSI. The present example will be explained in a case of the embodiment 2, but a similar circuit can also be applied to the embodiment 1.

[0080] In FIG. 4, D latches 21, 22 and D latches 37, 38 are to respectively synchronize input signals DATA1 and DATA2 by a synchronization clock signal CLK for the entire circuit shown in FIG. 4.

[0081] An exclusive OR gate 23 and an inverter 24 are used as operation elements for detecting the change point in the logic level, based on the results obtained from the D latches 21, 22. The output of the exclusive OR gate 23 assumes a HIGH logic level in the presence of a change from the prior state, or a LOW logic level in the absence of a change. The output of the inverter 24 is opposite that of the exclusive OR gate 23 and assumes a LOW logic level in the presence of a change from the prior state, or a HIGH logic level in the absence of a change. These signals are used as control signals for a sequencer and a counter to be explained later.

[0082] AND gates 25, 26 and a JK latch 27 constitute a sequencer which is the nucleus of the present circuit. 4-bit binary counters 28, 29 can execute counting up to a maximum count of 255, by setting 8-bit data in the ports D0 to D7. A ripple carry detection AND gate 30 is used as an element for detecting the generation of a ripple carry by a counter overflow.

[0083] An inverter 31, AND gates 32, 33, an OR gate 34 and a D latch 35 function as a selector for selecting latching and holding, wherein the D latch 35 captures the output of the D latch 22 when the output of the ripple carry detecting AND gate 30 is at the LOW logic level, but captures the output of the D latch 22 by feedback in order to hold the previous value when the aforementioned output is at the HIGH logic level. The output of the D latch 35 constitutes a new noise-eliminated signal NDATA1 (New DATA1). More specifically, the output of the D latch 35 assumes, at a timing where the input signal DATA1 continues a same logic level after a change there in, thus changed logic level of the input signal DATA1 but, in any other timing, maintains the prior logic level. Therefore the change in the logic level takes place only in a timing where the noise is not generated, so that the entry of the noise into the succeeding circuits can be prevented.

[0084] The synchronization circuit for the input signal DATA2 consisting of the latches 37, 38 and the selector circuit for selecting latching or holding, consisting of the inverter 39, the AND gates 40, 41, the OR gate 42 and the D latch 43 is provided for capturing the input signal DATA2, and the timing of latching is same as that for the input signal DATA1. Thus the synchronized signal of the input signal DATA2 is captured in case the output of the ripple carry outputting AND gate 30 is at the LOW logic level, but the prior value is held when the aforementioned output is at the HIGH logic level. The output of the D latch 43 constitutes a new noise-eliminated signal NDATA2 (New DATA2).

[0085] The output signal of the exclusive OR gate 36 is supplied to ENP input ports of counters 28, 29 in order to cause the counters 28, 29 to count whether a same logic level is continued for the predetermined time after the change in the logic level. This output signal is constituted by an exclusive OR logic of the finally outputted signal NDATA1 an the synchronized signal of the input signal DATA1. More specifically, the output signal of the exclusive OR gate 36 assumes the HIGH logic level, thereby permitting the count-up operation of the counters 28, 29 in case the currently outputted signal NDATA1 and the input signal DATA1 are at the different logic levels, namely if the input signal DATA1 shows a change and thereafter continues the changed level.

[0086] In the following there will be explained the entire control flow, principally based on the and gates 25, 26 and the JK latch 27 constituting the sequencer.

[0087] At first a signal CLR is momentarily lowered to the LOW level to reset the latches. In this state, as an input of the AND gate 25 (at the output of the exclusive OR gate 23) is at the LOW level, the Q output of the latch 27 is at the LOW level. Therefore the Q output of the JK latch 27 is fixed at the LOW level, and the JK latch 27 waits that the output of the exclusive OR gate 23 changes to the HIGH level.

[0088] If the logic level of the input signal DATA1 is different from that at an immediately proceeding CLK, such difference is recognized as a change point whereby the exclusive OR gate 23 outputs a HIGH level while the inverter 24 outputs a LOW level. In response the sequencer proceeds to a next step whereby the Q output of the JK latch 27 is changed to HIGH. The values at D0 to D7 are loaded into the counters 28, 29 and the count-up operation is started from the loaded value. The count-up operation is permitted by the output of the exclusive OR gate 36, which outputs a HIGH level thereby giving permission when the logic level of the input DATA1 is changed.

[0089] Thereafter the sequence waits that the output of the ripple carry output AND gate 30, constituting an input to the AND gate 26, changes to the HIGH level, namely continues to observe whether the same logic level is continued until the predetermined count-up operation is completed. If the count-up operation is interrupted by a noise, the output of the exclusive OR gate 24 changes to the HIGH level while the output of the inverter 24 changes to the LOW level, whereby the counters reset the values D0 to D7. Thus, the output of the inverter 24, receiving the output of the exclusive OR gate 23, is shifted to the LOW level, whereby the counters are reloaded and restart the count-up operation starting from the predetermined value. In this manner there is observed whether the same logic level is continued for the predetermined time.

[0090] Upon counting up the predetermined value, the output of the ripple carry output AND gate 30 whereupon the sequence proceeds to a next step.

[0091] Also such upshift of the output of the ripple carry output AND gate 30 to the HIGH level constitutes a permission signal for the AND gates 33, 41, whereby the outputs of the D latches 32, 38 are respectively captured in the D latches 35, 43 (with a level change of the signals NDATA1, NDATA2). In any other timing, the output of the ripple carry output AND gate 30 is at the LOW level, whereby the logic levels of the signals NDATA1, NDATA2 are maintained. Thus the sequencer returns to the original state (where the Q output of the JK latch 27 is at the LOW level), and awaits a next change point. As explained in the foregoing, the circuit shown in FIG. 4 can realize the function of the noise elimination unit 7 (FIG. 3).

[0092] In the above-described embodiment of the present invention, the noise elimination unit 7 considers the input signal as effective only if the input signal, after a change in the logic level, continues to maintain the changed level for the predetermined time. It is thus possible to securely eliminate the noise without significantly reducing the frequency of the communication clock signal, and also to reduce the magnitude of the circuits since the noise eliminating circuit is not required individually for the plural input signals. The communication apparatus of the foregoing embodiments 1 and 2 can be advantageously applied to the communication between the image forming apparatus and the two-sided unit (or another optional unit such as an MPT (multipurpose tray) or an envelope feeder) as shown in FIGS. 11 and 12. In such case, the above-described noise elimination unit 7 is provided at least on either of the image forming apparatus and the optional unit.

[0093] [Third Embodiment]

[0094]FIG. 5 is a view showing an example of the configuration of an image forming apparatus provided with a serial communication noise eliminating apparatus in which the present embodiment 3 is applicable.

[0095] Referring to FIG. 5, an image forming apparatus 100 is provided with a scanner unit 61 including a light source unit, a cylindrical lens, a scanner motor having a rotary polygon mirror, an imaging lens, a beam detector (BD) etc., a photosensitive member 62 to be exposed to a laser light emitted from the scanner unit 61, a developing unit 63 for developing a latent image formed by exposure of the photosensitive member 62, a transfer belt 65 for transferring an image on a recording sheet 64, a fixing unit 66 for fixing the transferred image to the recording sheet 64, a cassette 67 containing a stack of the recording sheets 64, and an engine control unit 1 for controlling the various units. The laser light emitted from the scanner unit 61 is focused on the photosensitive member 62 provided on a rotary drum. The latent image formed on the photosensitive member 62 by exposure to the laser light is developed into a visible image by the developing unit 63 containing developer. The visible image is transferred to the recording sheet 64, supplied from the cassette 67, on the transfer belt 65, and is subsequently fixed to the recording sheet in the fixing unit 66, and the recording sheet bearing the fixed image is finally discharged to an unrepresented discharge unit.

[0096] To the above-described image forming apparatus 100, there can be mounted a two-sided unit 68 enabling two-sided printing on the recording sheet 64, and such two-sided unit is provided with a two-sided unit control unit 69 for controlling the two-sided unit. When a two-sided printing is instructed, the recording sheet 64 after printing on the front surface thereof is guided to the two-sided unit 68, in which the recording sheet 64 is reversed, and is then fed again for printing on the rear surface of the recording sheet 64.

[0097] In such operation, the engine control unit 1 and the two-sided unit control unit 69 share the controls through mutual serial communication, and the two-sided unit control unit 69 controls the two-sided unit while the engine control unit 1 executes control of other units.

[0098]FIG. 6 is a block diagram showing connection of the engine control unit 1 and the two-sided unit control unit 69 by serial communication. The engine control unit 101 is provided with a master CPU 2 including a serial communication unit 3 for executing clock synchronized communication with the two-sided unit control unit 69 and a noise elimination unit 4 composed of a digital noise filter, while the two-sided unit control unit 69 is provided with a slave CPU 5 including a serial communication unit 6 for executing clock synchronized communication with the engine control unit 101, and a noise elimination unit 7 composed of a digital noise filter. The noise elimination unit 7 is composed of a digital noise filter and is similar in configuration to the noise elimination unit 7 shown in FIG. 3. In FIG. 6, components equivalent to those in FIG. 3 are therefore indicated by same number and will not be explained further. Also the noise elimination unit 4 is partially similar to the noise elimination unit 7, so that the corresponding components of the unit 4 are represented by same numbers as in the unit 7 and will not be explained further.

[0099]FIGS. 7A to 7C are views showing the relationship of clock signals and data signals in the clock synchronized serial communication.

[0100] In the following there will be explained the function of the configuration shown in FIG. 6, with reference also to FIGS. 7A to 7C. In FIGS. 7A to 7C, a communication synchronization clock signal sCLK is subjected to noise elimination by the noise elimination unit 7 to obtain a communication synchronization clock signal NsCLK. There are also shown a reception data signal sR×D, a reception data signal NsR×D after noise elimination by the noise elimination unit 7, and a signal LATCH*/HOLD for selecting whether to latch, by the latch/hold units 13, 15, a newly sampled input signal obtained by the data capture timing generation unit 12 or to hold the previous state by feedback. At the LOW or HIGH state of the LATCH*/HOLD signal, the latch/hold units 13, 15 respectively latch the newly sampled input signal or hold the previous state by feedback.

[0101]FIG. 7A shows a case where noises A, B are superposed in a period where the communication synchronization clock signal sCLK is not generated. In such case, as explained in the foregoing embodiments 1 and 2, the noises A and B are recognized as change points in the logic level, but are eliminated by the noise elimination unit 7 since a same logic level is not continued for the predetermined time (in the communication synchronization clock signal NsCLK and the reception data signal NsR×D).

[0102] In the following there will be explained a case with noises C, D as shown in FIG. 7B, in which the noise C occurs immediately after the inversion of the logic level of the communication synchronization clock signal NsCLK. As in the noises A and B shown in FIG. 7A, the noise C is recognized as a change point in the logic level, but is eliminated by the noise elimination unit 7 since a same logic level is not continued for the predetermined time (in the communication synchronization clock signal NsCLK and the reception data signal NsR×D).

[0103] The noise D occurs immediately after the inversion of the logic level of the communication synchronization clock signal sCLK. Thus, in case the noise D occurs after the inversion of the logic level of the communication synchronization clock signal sCLK but during the succeeding continued observation during the predetermined time, the noise elimination unit 7 does not invert the logic level of the communication synchronization clock signal NsCLK during the occurrence of the noise D since the same level is not maintained for the predetermined time after the change point of the logic level. At the end of the noise D, there is again recognized the change point in the logic level of the communication synchronization clock signal sCLK, and is then observed whether the same logic level is maintained for the predetermined time, and, after the lapse of the predetermined time, the latch/hold units 13, 15 latch the sampled data (communication synchronization clock signal sCLK after the change) (in the communication synchronization clock signal NsCLK and the reception data signal NsR×D).

[0104] Since the predetermined time of observation is shorter than the half period of the communication synchronization clock signal, there can be achieved secure capture of the input signal with noise elimination, though there is a certain delay in time. However such delay in time becomes no longer negligible, if the duration of the noise becomes longer or the frequency of the synchronization clock signal becomes higher.

[0105] In the foregoing there has been explained the operation of data reception by the slave side. In the following there will be explained the operation of data transmission by the slave side.

[0106] Referring to FIG. 8, the master side transmits a communication synchronization clock signal CLK and a transmission data signal T×D in synchronization with the communication synchronization clock signal CLK. These signals are received as sCLK and sR×D at the slave side. In the slave side, the signals sCLK, sR×D are passed by the noise elimination unit 7 to constitute the signals NSCLK, NsR×D indicated by thicker liners. In succession, the slave side transmits a signal sT×D, in synchronization not with the communication synchronization clock signal CLK but with the noise-eliminated communication synchronization clock signal NSCLK. It is thus possible to avoid transmission of the sT×D signal at an erroneous timing resulting from a noise. The sT×D signals is received at the master side as a signal R×D, which is then passed by the noise elimination unit 4 to constitute a signal NR×D indicated by a thicker line. In the present embodiment, as explained in the foregoing, the data signal sT×D which is basically to be transmitted in synchronization with the received communication synchronization clock signal sCLK is transmitted in synchronization with the communication synchronization clock signal NsCLK which is not necessarily synchronized with the clock signal sCLK.

[0107] If the receiving unit of the slave side has a predetermined continuation observation time t1 and that of the master side has a predetermined continuation observation time t2, the noise elimination unit 7 generates a delay at least by t1 in obtaining the noise-eliminated communication synchronization clock signal NsCLK by receiving the communication synchronization clock signal sCLK from the master side. Then the slave CPU 5 transmits the transmission data signal sT×D in synchronization with the communication synchronization clock signal NsCLK which is delayed by t1. When the master CPU 2 receives such data signal sT×D (=R×D), the noise elimination unit 4 generates a delay at least by t2. Therefore, with respect to the communication synchronization clock signal CLK (=sCLK), the reception data signal R×D is delayed by at least t1+t2.

[0108] In the present embodiment, the master CPU 2 transmits the data at the downshift of the communication synchronization clock signal CLK, and receives the data signal at the upshift of the communication synchronization clock signal CLK. Therefore, the aforementioned delay t1+t2 has to be accommodated at least in a half cycle period of the communication synchronization clock signal CLK. Stated differently, a condition t1+t2≦T/2, wherein T is the cycle period of the communication synchronization clock signal.

[0109] In case the continuation observation times t1, t2 at the slave and master sides are selected equal (t=t1=t2) in order to increase the noise resistance, there stands a relation 2×t≦T/2, so that;

t≦T/4.

[0110] Consequently, the aforementioned predetermined time for observation has to be equal to or less than ¼ of the period of the communication synchronization clock signal.

[0111] Also in consideration of a case where the delay time exceeds the aforementioned time t1 or t2, as in the noise D in FIG. 7B or a delay in the signal transmission, the continuation observation time is preferably about ⅛ of the cycle period of the communication synchronization clock signal. Also, since the master CPU 2 is at least aware of the predetermined time t2 in the noise elimination unit 4, it may receive the noise-eliminated reception data signal NR×D not in synchronization with the communication synchronization clock signal CLK but at a timing obtained by delaying the communication synchronization clock signal CLK by at least the aforementioned predetermined time t2.

[0112]FIG. 7C shows a case where a noise E continues while the logic level of the communication synchronization clock signal maintains a same level after a change. In such case, after the change point by the noise is recognized, there cannot be recognized a state of continuation of a same level for the predetermined time, so that the proper data reception cannot be executed. In case of such error, it is possible to include error correction data in the data themselves, thereby causing the CPU's 2, 5 to execute error correction. It is also possible to recognize an error for example by a parity check and to automatically determine the frequency of the communication synchronization clock signal.

[0113] [Fourth Embodiment]

[0114]FIG. 9 shows a variation of the engine control unit 1 and the two-sided unit control unit 69, wherein shown are a master CPU 16 including a serial communication unit 3 and a noise elimination unit 4 therein, and a slave CPU 17 including a serial communication unit 6 and a noise elimination unit 7 therein.

[0115] In the engine control unit 1 and the two-sided unit control unit 69 shown in FIG. 6, the digital noise elimination unit is constructed separately from the CPU, but, in the present variation, the noise elimination unit 4 or 7 is provided inside the CPU to achieve a further cost reduction.

[0116] Also time setting pins need not be provided outside the master CPU 16 and the slave CPU 17, by assigning the predetermined time, to be set or changed by the same level continuation observation time setting unit 11, to registers in the master CPU 16 and the slave CPU 17 and by accessing to the specified addresses in such registers, whereby a further cost reduction can be attained.

[0117] In the foregoing embodiments 3 and 4, there has been explained bidirectional data communication in synchronization with the communication synchronization clock signal from the master side, but the present invention is also applicable to a case where the communication synchronization clock signal is transmitted from the two-sided unit. Also the foregoing embodiments have been explained by an internal communication between the engine control unit 1 and the two-sided unit 69, but the present invention is not limited to such case and is applicable to the serial communication of various systems, for example with other optional units such as an MPT or an envelope feeder.

[0118] As detailedly explained in the foregoing, the noise elimination apparatus as described in the claim 1 and the clock synchronized serial communication apparatus as described in the claim 2 allow, in case of applying a variable digital noise filter to each input unit of plural digital inputs and a first input digital signal has a higher frequency than that of a second digital input signal and in case the change point of the state of the first digital input signal is same as that of the second digital input signal, to unify the circuit for generating the timing of capturing the signal state by capturing the second digital input signal at the time of capturing the first digital input signal, thereby reducing the magnitude of the circuits.

[0119] Also according to the present invention, in the noise elimination apparatus of a type observing the state of the input signal plural times at a predetermined time interval and capturing the signal state only in case, after a change in the signal state, the changed state is maintained for a predetermined time, the aforementioned predetermined time is set equal to or less than ¼ of the cycle period of the communication synchronization clock signal. It is thus no longer necessary to consider the delay in time specific to the digital noise filter, which can thus be utilized as the noise elimination apparatus for serial communication.

[0120] The present invention is not limited to the foregoing embodiments and is subject to various modifications and alterations within the scope and spirit of the appended claims. 

What is claimed is:
 1. A communication apparatus comprising: first input means for inputting a first digital signal; second input means for inputting a second digital signal synchronized with said first digital signal; observation means for observing the state of said first digital signal; first digital signal capture means for capturing said first digital signal, in case of a change in the state thereof, based on the state of said first digital signal for a predetermined time after said change; and second digital signal capture means for capturing said second digital signal at the capture timing for said first digital signal by said first digital signal capture means.
 2. An apparatus according to claim 1 ,, wherein said first digital signal is a clock signal, and said second digital signal is a data signal transmitted in synchronization with said clock signal.
 3. An apparatus according to claim 1 , further comprising setting means for variably setting said predetermined time.
 4. An image forming apparatus provided with a communication apparatus for communicating with a unit connected with said image forming apparatus, the communication apparatus comprising: first input means for inputting a first digital signal; second input means for inputting a second digital signal synchronized with said first digital signal; observation means for observing the state of said first digital signal; first digital signal capture means for capturing said first digital signal, in case of a change in the state thereof, based on the state of said first digital signal for a predetermined time after said change; and second digital signal capture means for capturing said second digital signal at the capture timing for said first digital signal by said first digital signal capture means.
 5. An apparatus according to claim 4 , wherein said unit is at least one of a two-sided unit, an MPT (multipurpose tray) and an envelope feeder, and said image forming apparatus communicates with a unit or plural units.
 6. A unit connected with an image forming apparatus and provided with a communication apparatus for communicating with said image forming apparatus, the communication apparatus comprising: first input means for inputting a first digital signal; second input means for inputting a second digital signal synchronized with said first digital signal; observation means for observing the state of said first digital signal; first digital signal capture means for capturing said first digital signal, in case of a change in the state thereof, based on the state of said first digital signal for a predetermined time after said change; and second digital signal capture means for capturing said second digital signal at the capture timing for said first digital signal by said first digital signal capture means.
 7. A unit according to claim 6 , wherein said unit is any of a two-sided unit, an MPT and an envelope feeder.
 8. An image forming system including an image forming apparatus and a unit connected to said image forming apparatus, wherein at least either of said image forming apparatus and said unit comprises a communication apparatus including: first input means for inputting a first digital signal; second input means for inputting a second digital signal synchronized with said first digital signal; observation means for observing the state of said first digital signal; first digital signal capture means for capturing said first digital signal, in case of a change in the state thereof, based on the state of said first digital signal for a predetermined time after said change; and second digital signal capture means for capturing said second digital signal at the capture timing for said first digital signal by said first digital signal capture means; and wherein communication is executed between said image forming apparatus and said unit utilizing said communication apparatus.
 9. A communication method in a communication apparatus including first input means for inputting a first digital signal and second input means for inputting a second digital signal synchronized with said first digital signal, the method comprising: an observation step of observing the state of said first digital signal; a first digital signal capture step of capturing said first digital signal, in case of a change in the state thereof, based on the state of said first digital signal for a predetermined time after said change; and a second digital signal capture step of capturing said second digital signal at the capture timing for said first digital signal by said first digital signal capture step.
 10. A method according to claim 9 ; wherein said first digital signal is a clock signal, and said second digital signal is a data signal transmitted in synchronization with said clock signal.
 11. A communication apparatus capable of transmitting a data signal in synchronization with an input clock signal, comprising: clock signal input means for inputting a clock signal; data signal transmission means for transmitting a data signal; observation means for observing the state of said clock signal; and clock signal capture means for capturing said clock signal, in case of a change in the state of said clock signal, based on the state of said clock signal for a predetermined time after said change; wherein said data signal transmission means transmits said data signal in synchronization with the clock signal captured by said clock signal capture means.
 12. An apparatus according to claim 11 , wherein said predetermined time is set equal to or less than ¼ of the cycle period of said clock signal.
 13. An apparatus according to claim 11 , further comprising setting means for variably setting said predetermined time.
 14. An image forming apparatus provided with a communication apparatus communicating with a unit connected to said image forming apparatus, the communication apparatus comprising: clock signal input means for inputting a clock signal; data signal transmission means for transmitting a data signal; observation means for observing the state of said clock signal; and clock signal capture means for capturing said clock signal, in case of a change in the state of said clock signal, based on the state of said clock signal for a predetermined time after said change; wherein said data signal transmission means transmits said data signal in synchronization with the clock signal captured by said clock signal capture means.
 15. An apparatus according to claim 14 , wherein said unit is at least one of a two-sided unit, an MPT and an envelope feeder, and said image forming apparatus communicates with a unit or plural units.
 16. A unit connected to an image forming apparatus and comprising a communication apparatus including: clock signal input means for inputting a clock signal; data signal transmission means for transmitting a data signal; observation means for observing the state of said clock signal; and clock signal capture means for capturing said clock signal, in case of a change in the state of said clock signal, based on the state of said clock signal for a predetermined time after said change; wherein said data signal transmission means transmits said data signal in synchronization with the clock signal captured by said clock signal capture means; and wherein said communication apparatus is used for communication with said image forming apparatus.
 17. A unit according to claim 16 , wherein said unit is any of a two-sided unit, an MPT and an envelope feeder.
 18. An image forming system including an image forming apparatus and a unit connected to said image forming apparatus, wherein at least either of said image forming apparatus and said unit includes a communication apparatus including: clock signal input means for inputting a clock signal; data signal transmission means for transmitting a data signal; observation means for observing the state of said clock signal; and clock signal capture means for capturing said clock signal, in case of a change in the state of said clock signal, based on the state of said clock signal for a predetermined time after said change; wherein communication is executed between said image forming apparatus and said unit, utilizing said communication apparatus.
 19. A communication method in a communication apparatus including digital signal input means for inputting a digital signal and data signal transmission means for transmitting a data signal, the method comprising: an observation step of observing the state of said first digital signal; a clock signal capture step of capturing said clock signal, in case of a change in the state of said clock signal, based on the state of said clock signal for a predetermined time after said change; and a data signal transmission step of transmitting said data signal in synchronization with the clock signal capture in said clock signal capture step.
 20. A method according to claim 19 , wherein said predetermined time is set equal to or less than 1/4 of the cycle period of said clock signal. 